Recent developments in networking industry (e.g., data-center, cloud, etc.) may present new challenges to the networking system development. One of the challenges is to meet stringent low latency targets in packet processing (e.g., with a limited set of features). The other challenge may be to diversify the product (e.g., a switch or a router) by making it behaviorally different, for example, in terms of an important parameter such as latency.
The existing switch or router chip architectures may be rich in networking features and may cater to some high bandwidth requirements. However, to address the low-latency requirements of specific markets, the chip architecture has to be modified to suppress a number of features to satisfy the low-latency requirements. The market segments where networking features are important within a relaxed latency requirement may be addressed by a different family of chips. The complexity involved in suppressing a feature in the existing chip is high, which can lead to increased bond-out options for a given chip. Further, there may be a repetition in the feature-set supported across the families of the existing chips. In the existing switch or router chip architectures, the latency modes are hard-wired and cannot be dynamically tuned based on required criteria such as feature, port, SLAs, stages, and pipeline.